

-- @module : Counter5_tb
-- @author : ben
-- @date   : 14-Mar-2012


library ieee;
use ieee.std_logic_1164.all;

entity Counter5_tb is 
end Counter5_tb;     
        

architecture rtl of Counter5_tb is
               
signal clk : bit := '0';
               
component Counter5 port (
		clk : in bit;
		hold_al : in bit; -- active low
		clr_al : in bit;
		overFlow : out bit;
		count : out bit_vector(4 downto 0)
	);
end component;    

signal hold_al : bit := '1';
signal clr_al : bit := '1';
signal overFlow : bit;    
signal count : bit_vector(4 downto 0);       
   
begin  

	clk <= not clk after 30 ns;

	UUT : Counter5 port map (clk, hold_al, clr_al, 
	overFlow, count);


end rtl;








